Apply the J, K, and CLK waveforms of Figure 5-24 to the FF of Figure 5-25. Assume that ( = 1…

Apply the J, K, and CLK waveforms of Figure 5-24 to the FF of Figure 5-25. Assume that ( = 1 initially, and determine the waveform. orlange FIGURE 5-24 (a) Clocked J-K flip-flop that responds only to the positive edge of the clock; (b) waveforms. CHAPTER S/FLIP FLOPS AND RELATED DEVICES 5-7 CLOCKED J-K FLIP-FLOP OUTCOMES Upon completion of this section, you will be able to: • Identify the purpose of all J-Kinput combinations. • Differentiate between a J-K and S-R FF. For any change in inputs, J, K, clk, predict the output state on Q. Figure 5-24(a) shows a clocked J-K flip-flop that is triggered by the positiva going edge of the clock signal. The J and K inputs control the state of the FF in the same ways as the Sand R inputs do for the clocked S-R flip-fl. except for one major difference: the J-K-1 condition does not result in an ambiguous autour. When I and K are both 1, the FF will always go to the opposite state upon the positive transition of the clock signal. This is called the toggle mode of operation. In this mode, if both ) and K are left HIGH the FF will change states (togale) for each PGT of the clock. The function table in Figure 5-24(a) summarizes how the J-K flip-flon responds to the PGT for each combination of J and K. Notice that the func tion table is the same as for the clocked S-R flip-flop (Figure 5-20) except for the K-1 condition. This condition results in Oo, which means that the new value of 0 will be the inverse of the value it had prior to the PGT; this is the toggle operation. Q, (no change) Q. (loggies) FIG thar tive a b c d e f g h i k Rose Toggle Set Toggle change (b) Toggle FIGURE 5-24 (a) Clocked J-K flip-flop that responds only to the positive edge of the clock (b) waveforms SECTION 5-7/CLOCKED J-K FurFLOP 259 The operation of this FF is illustrated by the waveforms in Figure 5-24(b). Once again, we assume that the setup and hold time requirements are being met. 1. Initially all inputs are O. and the output is assumed to be 1; that is, Do = 1. 2. When the positive-going edge of the first clock pulse occurs (point a), the J = 0, K -1 condition exists. Thus, the FF will be reset to the Q=0 state. 3. The second clock pulse finds J – K = 1 when it makes its positive tran- sition (point c). This causes the FF to toggle to its opposite state, Q = 1. 4. At pointe on the clock waveform, J and K are both 0, so that the FF does not change states on this transition 5. At point 8. J-1 and K -0. This is the condition that sets to the 1 state. However, it is already 1, and so it will remain there. 6. At point i, J-K=1, and so the FF toggles to its opposite state. The same thing occurs at point k. Note from these waveforms that the FF is not affected by the negative. going edge of the clock pulses. Also, the J and K input levels have no effect except upon the occurrence of the PGT of the clock signal. The J and K inputs by themselves cannot cause the FF to change states. Figure 5-25 shows the symbol for a clocked J-K flip-flop that triggers on the negative-going clock-signal transitions. The small circle on the CLK input indicates that this FF will trigger when the CLK input goes from 1 to 0. This FF operates in the same manner as the positive-edge FF of Figure 5-24 except that the output can change states only on negative-going clock-signal transitions (points b, d, f, h, and j). Both polarities of edge-triggered J-K flip- flops are in common usage. The J-K flip-flop is much more versatile than the S-R flip-flop because it has no ambiguous states. The J = K = 1 condition, which produces the toggling operation, finds extensive use in all types of binary counters. In essence, the J-K flip-flop can do anything the S-R flip-flop can do plus oper ate in the toggle mode. FIGURE 5-25 J.K flip-flop Bat triggers only on nega- ging transitions Ja JK CLK | opa L Qno change) r Q, loggies) Internal Circuitry of the Edge-Triggered J-K Flip-Flop of the internal circuitry of an adv anced